1. Field of the Invention
The present invention relates to an image formation apparatus such as a color laser beam printer using a plurality of laser scanning units (LSU). More particularly, the present invention relates to a video clock generation apparatus and a method of removing distortions, such as, errors in video clock signals, produced at the time of generating the video clock signals to compensate for color registration and an offset in laser scanning units of an image formation apparatus.
2. Description of Related Art
A conventional image formation apparatus, such as a color laser beam printer, includes a ring oscillator, a video clock generation apparatus, a control logic unit, and a multiplexer.
The ring oscillator generates a predetermined oscillation frequency. The video clock generation apparatus uses the oscillation frequency generated by the ring oscillator to generate a video clock signal. The control logic and the multiplexer are responsible for preventing errors, such as clock errors preceding and following an effective video clock period required to form images during the appropriate video clock signals.
The video clock generation apparatus may generate an abnormal video clock signal when attempting to stabilize the loopspeed signal to generate video clock signals. In addition, an abnormal video clock signal is also generated due to the initialization of the video clock signals for rearranging the main scanning direction of the image formation after the effective video clock period. Some video clock signals, in which the errors are produced during the generation of the video clock signals, cause a negative effect on the operations involving image data and processing image formation data, so that such abnormal video clock signals may cause severe image distortion to the image.
Conventionally, the control logic and the multiplexer have been used to convert front-end and back-end video clock signals into system clock signals to remove errors produced during a front-end video clock period preceding the effective video clock period and a back-end video clock period following the effective video clock period, so that the video clock signals can be generated without errors.
FIG. 1 is a timing diagram showing an example of a conventional system clock (SysClk) and video clock signals (VClk1 and VClk2). As shown in FIG. 1, the system clock SysClk is periodically generated, and the first video clock signal VC1k1 is generated by the video clock generation apparatus. Clock errors corresponding to an abnormal video clock are produced in the front-end and back-end video clock periods of the first video clock signal VC1k1. To remove the errors, the control logic generates the second video clock signal VClk2 by converting the first video clock signal VC1k1 during the front-end and back-end video clock periods to match the system clock SysClk.
Alternatively, the conversion of the front-end and back-end video clock signals into the system clock signals may produce errors. Therefore, there is a problem in that the errors produced by the clock conversion may cause a malfunction in the resolution enhancement technology (RET) for processing images.